In order to reduce development costs of hardware and software of computer systems, it is highly desirable to specify a common architecture design among a series of designs. The common architecture specifies a user instruction set and other system facilities that several processor designs implement compatibly. The use of a common architecture allows the reuse of hardware and software designs across a number of distinct architecture designs that vary in performance, cost, memory capacity and other design parameters.
A scalable architecture is a series of hardware designs which allows for variance of the design parameters while simultaneously maintaining a common architecture. One of the design parameters which limits the degree to which an architecture is scalable is the word size of the instruction set.
The word size of the instruction set is the number of bits of width of operands in the operations specified by the instruction set. Most processors utilize a word size that is a power of two, such as 16, 32, 64, or even 128 bits. The word size of some instructions may be different than others. For example, a processor may have some instructions with a 16 bit word size and others that have a 32 bit word size, where the word size is decoded from the instruction code, such as the Motorola 68000.
The data path size is the number of bits of width of operands which are taken in parallel in a data path to perform the operations specified by the instruction set.
The data path size is generally equal to the maximum word size in many implementations. When the word size varies, such an implementation leaves a portion of the data path unused or useless computing a value which is not stored. However some designs, such as the Motorola 68000, which has a 32-bit word size, implement the processor with a 16-bit data path. Such a design requires multiple execution cycles to perform 32-bit word size instructions.
When the data path size is equal to the maximum word size, performance is optimized, but instructions which use less than the maximum word size are not performed with the best possible efficiency, because the circuits which are not employed in the computation consume power and circuit area. When the data path size is less than the maximum word size, less circuit area is used, and the performance and power is directly proportional to the word size. Consequently, the latter design has lower price and power, but lower performance.
When small two's complement values appear as operands or results in a processor with a wide word size, many of the high order bits of these operands will be identical to the sign bit. However, if successive values of operands or results change the sign of the value, many bits change value. These changing values can result in substantial use of power in CMOS or other implementation technologies that consume power primarily on signal transitions.
Thus, there exists a need for a method and apparatus for dynamically varying the word size of the data paths and various control paths in accordance with the size of the operands so as to eliminate the foregoing problems and increase overall efficiency and performance.